Integrated circuits (ICs), such as ultra-large-scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). Such transistors can include semiconductor gates disposed above a channel region and between source and drain regions. The source and drain regions are typically heavily doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous).
As transistors become smaller, it is desirous to increase the charge carrier mobility in the channel region. Increasing charge carrier mobility increases the switching speed of the transistor. Channel regions formed from materials other than silicon have been proposed to increase charge carrier mobility. For example, conventional thin film transistors which typically utilize polysilicon channel regions have been formed on a silicon germanium (Si—Ge) epitaxial layer above a glass (e.g., SiO2) substrate. The Si—Ge epitaxial layer can be formed by a technique in which a semiconductor thin film, such as an amorphous silicon hydride (a-Si:H), an amorphous germanium hydride (a-Ge:H), or the like is melted and crystallized utilizing irradiation of pulse laser beams.
In a bulk type device, such as a metal oxide semiconductor field effect transistor (MOSFET), the use of Si—Ge materials can be used to increase charge carrier mobility, especially for hole-type carriers. A tensile strained silicon channel region, such as a silicon channel containing germanium, can have carrier mobility 2–5 times greater than a conventional Si channel region due to reduced carrier scattering and due to the reduced mass of holes in the germanium-containing material. According to conventional Si—Ge formation techniques for bulk-type devices, a dopant implant molecular beam epitaxy (MBE) technique forms a Si—Ge epitaxial layer. However, the MBE technique requires very complicated and expensive equipment, and is not feasible for mass production of ICs.
Double gate transistors, such as vertical double gate silicon-on-insulator (SOI) transistors or FinFETS, have significant advantages related to high drive current and high immunity to short channel effects. An article by Huang, et al. entitled “Sub-50 nm FinFET: PMOS” (1999 IEDM) discusses a silicon transistor in which the active layer is surrounded by a gate on two sides. However, double gate structures can be difficult to manufacture using conventional IC fabrication tools and techniques. Further, patterning can be difficult because of the topography associated with a silicon fin. At small critical dimensions, patterning may be impossible.
By way of example, a fin structure can be located over a layer of silicon dioxide, thereby achieving an SOI structure. Conventional FinFET SOI devices have been found to have a number of advantages over devices formed using semiconductor substrate construction, including better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions. While the conventional FinFET SOI devices provide advantages over MOSFETs formed on bulk semiconductor substrates due to its SOI construction, some fundamental characteristics of the FinFET, such as carrier mobility, are the same as those of other MOSFETs because the FinFET source, drain and channel regions are typically made from conventional bulk MOSFET semiconductor materials (e.g., silicon).
The fin structure of FinFET SOI devices can be located below several different layers, including a photoresist layer, a bottom anti-reflective coating (BARC) layer, and a polysilicon layer. Various problems can exist with such a configuration. The photoresist layer may be thinner over the fin structure. In contrast, the polysilicon layer may be very thick at the edge of the fin structure. The BARC may be thick at the edge of the fin structure. Such a configuration leads to large over-etch requirements for the BARC layer and the polysilicon layer. Such requirements increase the size of the transistor.
When manufacturing FinFET structures, it is desirous to have a fin channel structure with a high aspect ratio. A higher aspect ratio for the fin channel structure allows a larger amount of current to be provided through the same amount of topographical area. Heretofore, fabrication of high aspect ratio FinFETS has not been practicable for large-scale fabrication.
Thus, there is a need for an integrated circuit or electronic device that includes channel regions with higher channel mobility, higher immunity to short channel effects, and higher drive current. Further, there is a need for a method of patterning FinFET devices having small critical dimensions. Even further, there is a need for a method of fabricating strained silicon fin-shaped channels for FinFET devices. Yet further, there is a need for a high aspect ratio FinFET device. Even further still, there is a need for an efficient method of manufacturing a high aspect ratio fin structure. Further still, there is a need for a FinFET device with a strained semiconductor fin-shaped channel region. Yet even further, there is a need for a process of fabricating a FinFET device with a strained semiconductor fin-shaped channel.